ASUS P5E3 Deluxe Overclocking: DDR3 Takes Front Stage
by Kris Boughton on November 20, 2007 4:00 AM EST- Posted in
- CPUs
BIOS Setup and Tweaking, Continued
DRAM Static Read Control: Auto, Enabled, and Disabled. We were unable to affect any measurable performance change because of toggling this setting. This setting is curious by its very nature as Ai Transaction Booster (explained below) manipulates the MCH Static Read Control Delay setting directly, implying there would be no reason for this option.
DRAM Dynamic Write Control: Auto, Enabled, and Disabled. See above.
Ai Clock Twister: Auto, Light, Moderate, and Strong. This setting controls the number of memory access phases that are "pulled-in" to the next lower (higher performance) Static Read Delay value. In essence, this allows for smaller, incremental performance gains if the user is unable to achieve stability when using the next lower Static Read Delay value.
Ai Clock Skew for Channel A/B: This setting allows you to either advance or delay the signal timings for Channel A or Channel B DIMMs. Because it's not possible to locate all memory modules an equal distance from the MCH, it's important to be able to adjust signal timing to ensure all data (or requests for data) arrive at the same point at precisely the same time. When experimenting with this setting either slightly delay Channel A (since it's closer to the MCH) or advance Channel B - do not change both simultaneously unless you find you need more than 350ps (picoseconds) of total skew (highly unlikely).
Ai Transaction Booster: Auto, Enabled (Boost: 1-8), and Disabled (Relax: 1-8). This is probably one of the most important BIOS settings when it comes to extracting every possible bit of performance from the system. Setting these fields can improve total memory bandwidth up to 15% and produce a considerable reduction in access latency.
Static Read Control Delay, sometimes referred to as Performance Level, is a primary MCH "timing" value and has a rather significant impact on memory read performance as well as overall memory access latency. In case you are wondering why low access latency matters, we submit to you the following quick-and-dirty response: improved memory latency (courtesy of the Integrated Memory Controller/IMC) is the primary reason that AMD Athlon 64 chips have performed so well. Latency is one of the few areas where AMD maintains a lead over Intel, and Intel will move to an IMC design late next year (starting with Nehalem).
Much like primary memory timings, this MCH "timing" is measured in clock cycles and is relative to the base transmission frequency (2 x FSB). This explains why Static Read Control Delay should increase as FSB rates rise. Similar to memory timings, maintaining a lower value longer with the proper application of MCH voltage can lead to improved performance. In other words, "boosting" the Ai Transaction level may require a higher MCH voltage than would be otherwise required if a more relaxed level were set.
Because these settings effectively apply an offset to the default value it can sometimes be difficult to confirm exactly what is going on - it is almost like flying blind. Thankfully, a wonderful tool exists that reads and reports "Performance Level" from within Windows, allowing us to verify that the board is operating as intended. Memset 3.4 (beta 3), available as freeware, can be found through a simple search using your favorite search engine. Here we see Performance Level, as reported by Memset 3.4, as well as Command Rate and memory latency from EVEREST 4.20.
Auto allows the BIOS to set the values automatically which, through simple experimentation and observation, has been simplified to the following relationship: Static Read Control Delay (default) = tCL. Knowing this makes adjusting the value rather simple. Keep in mind that workable values are in the range of 1-3 (boost or relax) only; selecting values from 4 through 8 will always result in a POST failure.
For example, with memory set to DDR-1600 6-6-6-15, the BIOS will establish a default Static Read Control Delay of 6. Setting Ai Transaction Booster to Enabled with a Boost Level of 1 results in a final Static Read Control Delay setting of 6 - 1 = 5. Alternatively, selecting Disabled with a Relax Level of 1 results in a final value of 6 + 1 = 7. Just like in the case of memory timings, lower is tighter (higher performance).
Finally, a simple rule to keep in mind when setting Static Read Control Delay - 4 requires a CAS Latency (tCL) of 6 or lower, 5 requires a tCL of 7 or lower, and 6 requires a tCL of 8 or lower. There are no other known limitations at this time.
CPU Voltage: Maximum of 1.7000V. Our experience with the ASUS P5E3 Deluxe has shown a rather large voltage offset when it comes to VCore. For example, setting 1.4675V in the BIOS results in an in-Windows idle voltage of ~1.4250V by DMM. Under load we see the voltage settle out as low as 1.39V. While we understand the need and requirement for VDroop, a total difference in programmed BIOS voltage to full-load voltage of more than 0.07V is excessive. Keep this in mind when setting this value if you already know the minimum voltage your CPU needs for stable operation or utilize the load-line calibration setting listed below to reduce VDroop.
CPU PLL Voltage: Maximum of 2.78V. Out of all the voltages the user can manipulate this one is by far the most dangerous. Maximum vCPUpll, as established by Intel, is 1.60V (default for this board) making 2.78V a whopping ~75% over specification! (As an aside, this would be the equivalent of subjecting your 65nm CPU to a core voltage of over 2.5V). Exercise extreme caution when utilizing higher values as setting this value too high can result in the CPUs "losing cores" after being subjected to voltage in excess of ~2.0V. The good news is that we did not see an increase in overclocking potential with voltages above 1.68V.
DRAM Static Read Control: Auto, Enabled, and Disabled. We were unable to affect any measurable performance change because of toggling this setting. This setting is curious by its very nature as Ai Transaction Booster (explained below) manipulates the MCH Static Read Control Delay setting directly, implying there would be no reason for this option.
DRAM Dynamic Write Control: Auto, Enabled, and Disabled. See above.
Ai Clock Twister: Auto, Light, Moderate, and Strong. This setting controls the number of memory access phases that are "pulled-in" to the next lower (higher performance) Static Read Delay value. In essence, this allows for smaller, incremental performance gains if the user is unable to achieve stability when using the next lower Static Read Delay value.
Ai Clock Skew for Channel A/B: This setting allows you to either advance or delay the signal timings for Channel A or Channel B DIMMs. Because it's not possible to locate all memory modules an equal distance from the MCH, it's important to be able to adjust signal timing to ensure all data (or requests for data) arrive at the same point at precisely the same time. When experimenting with this setting either slightly delay Channel A (since it's closer to the MCH) or advance Channel B - do not change both simultaneously unless you find you need more than 350ps (picoseconds) of total skew (highly unlikely).
Ai Transaction Booster: Auto, Enabled (Boost: 1-8), and Disabled (Relax: 1-8). This is probably one of the most important BIOS settings when it comes to extracting every possible bit of performance from the system. Setting these fields can improve total memory bandwidth up to 15% and produce a considerable reduction in access latency.
Static Read Control Delay, sometimes referred to as Performance Level, is a primary MCH "timing" value and has a rather significant impact on memory read performance as well as overall memory access latency. In case you are wondering why low access latency matters, we submit to you the following quick-and-dirty response: improved memory latency (courtesy of the Integrated Memory Controller/IMC) is the primary reason that AMD Athlon 64 chips have performed so well. Latency is one of the few areas where AMD maintains a lead over Intel, and Intel will move to an IMC design late next year (starting with Nehalem).
Much like primary memory timings, this MCH "timing" is measured in clock cycles and is relative to the base transmission frequency (2 x FSB). This explains why Static Read Control Delay should increase as FSB rates rise. Similar to memory timings, maintaining a lower value longer with the proper application of MCH voltage can lead to improved performance. In other words, "boosting" the Ai Transaction level may require a higher MCH voltage than would be otherwise required if a more relaxed level were set.
Because these settings effectively apply an offset to the default value it can sometimes be difficult to confirm exactly what is going on - it is almost like flying blind. Thankfully, a wonderful tool exists that reads and reports "Performance Level" from within Windows, allowing us to verify that the board is operating as intended. Memset 3.4 (beta 3), available as freeware, can be found through a simple search using your favorite search engine. Here we see Performance Level, as reported by Memset 3.4, as well as Command Rate and memory latency from EVEREST 4.20.
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Auto allows the BIOS to set the values automatically which, through simple experimentation and observation, has been simplified to the following relationship: Static Read Control Delay (default) = tCL. Knowing this makes adjusting the value rather simple. Keep in mind that workable values are in the range of 1-3 (boost or relax) only; selecting values from 4 through 8 will always result in a POST failure.
For example, with memory set to DDR-1600 6-6-6-15, the BIOS will establish a default Static Read Control Delay of 6. Setting Ai Transaction Booster to Enabled with a Boost Level of 1 results in a final Static Read Control Delay setting of 6 - 1 = 5. Alternatively, selecting Disabled with a Relax Level of 1 results in a final value of 6 + 1 = 7. Just like in the case of memory timings, lower is tighter (higher performance).
Finally, a simple rule to keep in mind when setting Static Read Control Delay - 4 requires a CAS Latency (tCL) of 6 or lower, 5 requires a tCL of 7 or lower, and 6 requires a tCL of 8 or lower. There are no other known limitations at this time.
CPU Voltage: Maximum of 1.7000V. Our experience with the ASUS P5E3 Deluxe has shown a rather large voltage offset when it comes to VCore. For example, setting 1.4675V in the BIOS results in an in-Windows idle voltage of ~1.4250V by DMM. Under load we see the voltage settle out as low as 1.39V. While we understand the need and requirement for VDroop, a total difference in programmed BIOS voltage to full-load voltage of more than 0.07V is excessive. Keep this in mind when setting this value if you already know the minimum voltage your CPU needs for stable operation or utilize the load-line calibration setting listed below to reduce VDroop.
CPU PLL Voltage: Maximum of 2.78V. Out of all the voltages the user can manipulate this one is by far the most dangerous. Maximum vCPUpll, as established by Intel, is 1.60V (default for this board) making 2.78V a whopping ~75% over specification! (As an aside, this would be the equivalent of subjecting your 65nm CPU to a core voltage of over 2.5V). Exercise extreme caution when utilizing higher values as setting this value too high can result in the CPUs "losing cores" after being subjected to voltage in excess of ~2.0V. The good news is that we did not see an increase in overclocking potential with voltages above 1.68V.
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retrospooty - Friday, November 23, 2007 - link
I should have added that beyond the current Intel roadmap, they are looking at Rambus XDR for future CPU's. DDR and its minor generational bumps arent going to cut it for long. DDR4 and DDR5 arent much better, higher speeds and higher latencies all the way = very minor performance increases.I really wouldnt advise anyone, even the enthusiests to get DDR3 now, in 1 more year Nehalem will be out with 3 channel DDR and it will likely be faster, or lower latency and cheaper than current DDR3 is, and anyone who fancies themselves and "enthusiest" will be upgrading again at that point, because 3 channel DDR3 on top of Nehalems internal memory controller WILL give a notable performance increase.
jkostans - Tuesday, November 20, 2007 - link
Spending an extra $50-100 on a GPU is still way more effective than spending the $200-300 more for DDR3. The only games that struggle with framerate on a modern mid-high end system are mostly GPU and somewhat CPU dependent. You get about the least bang for your buck with memory, but at the bleeding edge of performance I guess money is not a barrier.TA152H - Tuesday, November 20, 2007 - link
Another way to look at it is, would you rather have 1 GB of DDR3 or 2 GB of DDR2? They cost roughly the same.I'd rather have the 1 GB, since I can add more memory later. If you end up with DDR2, your system is forever degraded by inferior memory. You can't add it later unless you get a new motherboard. Besides, faster memory makes everything run faster, more memory only makes things run faster if you have to page (pretty much, I know Microsoft steals memory for caching, but that's a mixed bag anyway). Also, more memory wants more power.
I can already hear the argument from people saying that you can get 1 GB of DDR2 as well, and still realize a cost saving. It's a valid point, but at 1 GB the cost difference isn't that great, and I think the performance, and future upgradeability still make DDR3 attractive for some people.
LoneWolf15 - Tuesday, November 20, 2007 - link
Another way to look at it is, would you rather have 4GB of high-performance DDR2 for $150 (or cheaper, my 4GB of Crucial Ballistix cost me $140 this summer and is cheaper yet now), or 2GB of DDR3 for $200?
The industry must really love folks like you, who buy into the marketing hype. DDR2 is far from inferior, or Intel wouldn't have been using it all this time, and saying your system will be "forever degraded" is ridiculous tripe.
DDR3 has more bandwidth, but isn't necessarily "faster" as it is higher latency. That $150 DDR2 I mentioned has a CAS latency of 4; the $200 2GB DDR3 has a CAS latency of 7. DDR3 will only be attractive once it gains market share, lowering its price. What with enough P35 boards and some X38 boards still supporting DDR2, there is no reason to switch.
TA152H - Tuesday, November 20, 2007 - link
DDR3 is faster, if you can't accept that much, you aren't worth arguing with. DDR2 is inferior, but it's cheaper.DDR2 was not inferior until DDR3 came out. Inferior is a relative term, there has to be something better. Is English not your first language?
natebsi - Tuesday, November 20, 2007 - link
Sheesh. Personal attack much?TA152H - Tuesday, November 20, 2007 - link
Actually, you don't think his rant was a personal attack? If you don't agree with some people, you are just listening to marketing hype, or don't understand this or that. Instead of realizing there are reasons for both DDR2 (cost and compatibility) and DDR3 (everything else), you get people who accuse you of not understanding anything, and just being part of some company's marketing machine. It's so uneducated and insulting, it warrants something of the same kind back.Anyone that thinks DDR3 is completely useless, even now, is an idiot. This type of person is not worth arguing with. They are both useful, right now, and the arguments should really be about the gray areas where they begin to overlap. I might think DDR3's area is a little bigger than most, but at least I recognize that there are many people that are better off with DDR2. By the same token, I expect people to have at least basic intelligence and recognize there are areas where DDR3 makes more sense, even now. Pure performance always has a place, especially when it costs only $500, or less, more.
aeternitas - Sunday, December 9, 2007 - link
Grats on being the article clown.yyrkoon - Thursday, November 22, 2007 - link
I think the point if entirely lost on you.First, you can for instance get the same overclocks from DDR2 memory(at least from what I've seen here, because even my Promos 800 sticks can hit 1:1 475Mhz FSB which is 10Mhz faster than what I saw in the benches here).
Secondly, a system with 4GB of DDR2 vs 1-2GB of DDR3 *will* be more responsive. You can argue about it all you want, until you're blue in the face, and the only thing you will prove is that you have no actual hands on experience. Yes, this is even on a system with a 32BIT OS.
Thirdly, remember all the discussion a while back about AMD systems not performing any better than the Intel C2D systems despite having faster memory capabilities?
Lastly, even the writer of this article said the differences between the DDR2, and DDR3 system was barely a whisper . . .
But, you're right, anyone claiming that DDR3 RIGHT NOW is useless is an idiot, because they obviously can not see the eManhood effect capabilities here in saying that they paid X amount more for DDR3 vs DDR2. Anyone who has bragged about their $3000 usd set of car rims being much better than the stock rims that came with the car can surely see this point.
Griswold - Tuesday, November 20, 2007 - link
Oh yea I bet DDR3 makes perfect sense in your basement "lab" where you run your benchmarks all day long. Instead of yapping like a chihuaha with a superiority complex, you could instead just provide some realworld applications that make DDR3 not look like a waste of money right here, right now with todays hardware.Future proofing my ass, get a clue.