ASUS P5E3 Deluxe Overclocking: DDR3 Takes Front Stage

General Memory Performance Scaling and Command Rate

Fiddling with the BIOS to see what works and what does not is all well and good but meaningless unless we have A way to quantify the results. To that end, we've done our best to tabulate the details of our testing and present the following.


Before delving into more advanced discussions let's first review what we already know about typical memory scaling. In this graph, we show how memory responds to a simple change in base operating frequency. Here we can see the memory responds just as we expect - higher frequencies bring about higher bandwidths.

The green lines represent actual data points, collected with timings of 8-8-8-15, a Static Read Control Delay of 7 and Command Rate 1N. The blue lines represent extrapolated data points - i.e. we did not measure these values directly but rather scaled existing test results to create additional information for comparison purposes. This is an important detail to note as this means we extrapolated the data points in the context of our original tests (the same timings, etc.). While this isn't 100% accurate, it does provide a very good estimate for the timings you would most likely set at these particular speeds.

The result is an unadulterated illustration of memory read performance with frequency being the only variable - just as we intended. This also gives us the ability to predict how our memory would perform should we run it at DDR-2000 with 8-8-8-15 timings. While some choose to do this by pumping excessive voltage through their memory modules, we feel our method is safer as we do not risk damaging our expensive DDR3. Future DDR3 will likely be able to reach these higher performance settings at more reasonable voltages, however.

Our ASUS P5E3 Deluxe exhibited an amazing memory scaling range, allowing us to run our memory 1:1 at stock speeds with tight 4-4-4-12 timings and as high as about DDR-1960 at 8-8-8-15 by using the more exotic 2:1 divider. It appears our final limitation was the board/CPU combination and not the memory. We have no doubt the memory would have continued to scale well above 2GHz had there been additional FSB headroom to play with.


In this analysis, intended to show the affect of 1N versus 2N Command Rate, we see that setting 1N (DRAM Command Rate to 1T) can improve synthetic memory read scores by as much as ~3.3% over 2N. Static Read Control Delay was held constant at 7 through the use of Ai Transaction Booster while both DDR3 memory frequency and timings were increased and Command Rate was forced to either 1N or 2N by BIOS.

We can conclude that DDR-1860, 8-8-8-15-CR1 is roughly the equivalent of DDR-1925, 8-8-8-15-CR2. This means modules that might not otherwise be able to reach the speeds necessary to provide the desired target bandwidth can take advantage of the performance enhancing capabilities of the MCH in order achieve this end. In most instances enabling Command Rate 1N did nothing to bring about early instability making this setting nothing more than free bandwidth for the taking. The source of the increased bandwidth comes from the addressing efficiency improvements that come with 1N commanding and the reduction in overall memory access latency.